ASIC Design/Verification Engineer

Salt; San Francisco (CA); Hybrid; USD 180,000 - 280,000; Full time

Job summary

Salt in Sunnyvale, CA, is seeking an ASIC Design and/or Verification Engineer (Sr. to Principal) to design, verify and optimize high-performance networking chips in a hybrid work model.

You will write Verilog/SystemVerilog, develop specs, mentor juniors, and collaborate with Physical Design to meet timing and power targets.

Candidates have 4–15+ years of relevant experience and a strong background in architecture, verification, and scripting with Perl or Python.

Qualifications

• Bachelor’s degree in Engineering; Master’s strongly desired.
• Experience leading high-performance subsystems from spec to final netlist.
• Knowledge of computer architecture and networking protocols.
• Strong Verilog/SystemVerilog coding skills from prior work.
• Knowledge of synthesis and lint tools used in ASIC flows.
• Excellent written and verbal communication skills.
• Proficiency in Perl/Python.

Responsibilities

• Architect/verify complex modules and subsystems for high-performance chips.
• Write detailed functional and micro-architecture specifications.
• Implement design/verification using Verilog or SystemVerilog.
• Write functional coverage/SVA to catch corner-case bugs.
• Ensure modules meet power targets using advanced power-reduction techniques.
• Work with Physical Design for timing closure and RTL timing fixes.
• Collaborate with Design/Verification to ensure full validation.
• Lead and mentor new graduates and interns.

Skills

Verilog/SystemVerilog

Leadership

Python/Perl

Communications

Synthesis/Lint

Education

Bachelor’s degree in Engineering

Master’s degree strongly desired

Tools

Synthesis tools

Job description

ASIC Design and/or Verification Engineers (Sr. to Principal)

Hybrid - Sunnyvale, CA

Job Family Definition:

Designs, analyzes, develops, modifies and evaluates components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication.

Responsibilities:

• Architect/verify complex modules and subsystems used in high performance networking chips.
• Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets.
• Implement the design/verification using Verilog or System Verilog
• Write functional coverage/SVA to help verification catch corner case bugs.
• Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
• Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.
• Collaborate with the Design/Verification team to make sure your block is fully validated.
• Show leadership and provide guidance to new college-grad/junior engineers and interns.

Recommended skills

• Bachelor’s degree in Engineering required (Master’s strongly desired) with 4-15+ years of relevant experience.
• Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist.
• Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
• Strong coding skills in Verilog/System Verilog through previous work experience are necessary.
• Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired.
• Excellent written and verbal communications skills is necessary.
• Knowledge of Perl/Python is strongly desired.