Senior ASIC Design Engineer — High-Speed Networking Chips

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 154,000 - 311,000; Full time

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA, onsite role focused on designing high-speed ASICs. You will develop micro-architecture from specs, implement RTL in Verilog/SystemVerilog, and drive verification with coverage and assertions.

You will work with Physical Design and Verification teams to meet timing and validation goals while mentoring new engineers. Join a fast-paced silicon group that builds leading networking chips, with opportunities to grow leadership skills and contribute to

Qualifications

• Bachelor’s in Electrical Engineering required; Master’s strongly preferred.
• Strong analytical and problem-solving skills are essential.
• Knowledge of computer architecture and networking protocols is a plus.
• Strong coding skills in Verilog/SystemVerilog through coursework or prior work.
• Familiarity with EDA tools, synthesis, and linting is desirable.
• Excellent written and verbal communication skills are beneficial.
• Perl/Python knowledge is a plus.
• Experience with AI agentic tools is a plus.

Responsibilities

• Develop a detailed micro-architecture specification from functional specs to meet power and area goals.
• Implement RTL design using Verilog or SystemVerilog.
• Write functional coverage and SystemVerilog Assertions for verification.
• Collaborate with Physical Design for floorplanning and timing closure; fix RTL timing to hit frequency targets.
• Coordinate with Verification to ensure full validation of the block.
• Mentor junior engineers and interns to develop leadership skills.

Skills

Verilog/SystemVerilog

Problem solving

Communication

Python/Perl

AI tools knowledge

Education

Bachelor’s degree in Electrical Engineering

Master’s degree strongly desired

Tools

EDA tools

Synthesis

Lint

Job description

Hewlett Packard Enterprise in Sunnyvale, CA, onsite role focused on designing high-speed ASICs. You will develop micro-architecture from specs, implement RTL in Verilog/SystemVerilog, and drive verification with coverage and assertions.

You will work with Physical Design and Verification teams to meet timing and validation goals while mentoring new engineers. Join a fast-paced silicon group that builds leading networking chips, with opportunities to grow leadership skills and contribute to