Senior ASIC Verification Engineer – Networking SoCs (Hybrid)

Hobbsnews; Sunnyvale, Northern (CA, KY); Hybrid; USD 150,000 - 310,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a highly motivated Senior ASIC Verification Engineer to join our Networking Silicon group in Sunnyvale, CA. You will own block-level verification and drive coverage closure, from test plans to final results, in a fast-paced environment.

You will develop advanced UVM environments, analyze results with Cadence Xcelium, Synopsys VCS, and Mentor Questa, and collaborate with cross-functional teams to deliver high-quality ASIC/SoC deliverables for networking

Qualifications

• 10+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

ASIC/SoC verification

SystemVerilog & UVM

Randomization & constraints

Test planning & debugging

Simulation tools (Xcelium/VCS/Questa)

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise is seeking a highly motivated Senior ASIC Verification Engineer to join our Networking Silicon group in Sunnyvale, CA. You will own block-level verification and drive coverage closure, from test plans to final results, in a fast-paced environment.

You will develop advanced UVM environments, analyze results with Cadence Xcelium, Synopsys VCS, and Mentor Questa, and collaborate with cross-functional teams to deliver high-quality ASIC/SoC deliverables for networking