Senior ASIC Verification Engineer (Hybrid)

HITEC; Sunnyvale, Northern (CA, KY); Hybrid; USD 159,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Verification Engineer to shape verification strategy for complex VLSI blocks in a hybrid work setting in California. The role leads teams, designs testbenches, and collaborates with SW and design peers to ensure robust ASICs.

You will start from a module spec to produce a test plan, write System Verilog/C/C++ models, and build test benches. Strong VLSI knowledge, UVM experience, and mentoring are essential.

Qualifications

• Bachelor's or Master's degree in EE/CE or equivalent.
• 6–10 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of VLSI principles, digital logic and architecture.
• Experience with SystemVerilog/UV M, UVM, and RTL verification.
• Proficiency in C/C++, Perl/Python as needed for verification.
• Excellent communication and leadership abilities.

Responsibilities

• Lead projects of VLSI engineers and partners through design, validation and testing.
• Review designs for compliance with VLSI guidelines and standards.
• Provide architecture guidance and cross-organization leadership.
• Mentor junior engineers and interns, drive technology innovation.
• Develop module/testbench verification and qualification for ASICs.

Skills

VLSI design

Verification

SystemVerilog

UVM

C/C++

Python

Digital logic

Computer architecture

Education

Bachelor's or Master's degree in Electrical Engineering

Computer engineering or equivalent

Tools

EDA tools

Debugging tools

Job description

Hewlett Packard Enterprise is seeking a Senior ASIC Verification Engineer to shape verification strategy for complex VLSI blocks in a hybrid work setting in California. The role leads teams, designs testbenches, and collaborates with SW and design peers to ensure robust ASICs.

You will start from a module spec to produce a test plan, write System Verilog/C/C++ models, and build test benches. Strong VLSI knowledge, UVM experience, and mentoring are essential.