Senior ASIC Design Engineer - Hybrid (2 days in office)

Hewlett Packard Enterprise; Roseville (CA); Hybrid; USD 159,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise is seeking an experienced ASIC engineer to join the HPE Networking Silicon group. You will develop high‑speed ASICs from specs to netlist, and work on complex modules and subsystems in a fast‑paced environment.

Responsibilities include creating micro‑architecture specs, coding in Verilog/SystemVerilog, writing functional coverage, coordinating with Physical Design and Verification, and mentoring new engineers.

Qualifications

• Bachelor’s degree in Electrical Engineering required; Master’s strongly desired.
• Strong analytical and problem solving skills are required.
• Knowledge of computer architecture and networking protocols is a plus.

Responsibilities

• Produce a detailed micro-architecture specification meeting power/area requirements.
• Implement the design using Verilog or SystemVerilog.
• Write functional coverage/SVA to verify corner case bugs.
• Collaborate with Physical Design for floorplanning and timing closure to meet frequency targets.
• Coordinate with Verification to ensure full validation of the block.
• Mentor new engineers and interns to develop leadership skills.

Skills

Verilog

SystemVerilog

Analytical thinking

Computer architecture

Python

Perl

AI tools

Education

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Tools

EDA tools

Synthesis tools

Job description

Hewlett Packard Enterprise is seeking an experienced ASIC engineer to join the HPE Networking Silicon group. You will develop high‑speed ASICs from specs to netlist, and work on complex modules and subsystems in a fast‑paced environment.

Responsibilities include creating micro‑architecture specs, coding in Verilog/SystemVerilog, writing functional coverage, coordinating with Physical Design and Verification, and mentoring new engineers.