Senior ASIC Design Engineer - Hybrid Networking Chips

Hewlett Packard Enterprise Development LP; Durham (NC); Hybrid; USD 140,000 - 321,000; Full time

Benefits offered by this job

Hybrid work

Career development

Inclusive workplace

Job summary

Hewlett Packard Enterprise Development LP seeks a Senior ASIC Design Engineer for its Durham, NC Silicon group. The role is hybrid, with in-office presence 2 days per week and US citizenship preferred.

You will architect modules for high-performance networking chips, write specs, and implement in Verilog/SystemVerilog while collaborating with physical design, verification, and power teams. Mentoring interns and new grads is also expected.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering required.
• Master’s degree strongly desired.
• 7+ years of relevant experience in ASIC design.

Responsibilities

• Architect complex modules and subsystems for high-performance networking chips.
• Write detailed functional and micro-architecture specifications.
• Implement designs using Verilog or SystemVerilog.

Skills

Analytical skills

Problem solving

Leadership

Networking protocols knowledge

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree preferred

Tools

Verilog

SystemVerilog

Job description

Hewlett Packard Enterprise Development LP seeks a Senior ASIC Design Engineer for its Durham, NC Silicon group. The role is hybrid, with in-office presence 2 days per week and US citizenship preferred.

You will architect modules for high-performance networking chips, write specs, and implement in Verilog/SystemVerilog while collaborating with physical design, verification, and power teams. Mentoring interns and new grads is also expected.