Senior ASIC Design Engineer — High-Speed Networking Chips

Hewlett Packard Enterprise Development LP; Roseville (CA); On-site; USD 159,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise in California seeks an experienced ASIC/SoC design engineer to develop high-speed networking chips. You will translate specifications into micro-architectures and implement RTL with Verilog/SystemVerilog, driving tight timing and power targets.

You will collaborate with Physical Design and Verification teams to ensure full validation and high-quality silicon. Leadership opportunities include mentoring interns and new grads within a fast-paced silicon group.

Qualifications

• Bachelor's in Electrical Engineering required; Master’s strongly preferred.
• 5+ years of relevant experience in ASIC/SoC design.
• Strong Verilog/SystemVerilog coding experience from courses or industry.
• Familiarity with synthesis, lint, and advanced EDA tools.
• Excellent written and verbal communication skills.

Responsibilities

• Start with a functional specification of a module and produce a detailed micro-architecture specification meeting power/area requirements.
• Implement the design using Verilog or System Verilog.
• Write functional coverage/SVA to help verification catch corner-case bugs.
• Collaborate with the Physical Design team for optimal floorplanning and timing closure; fix RTL timing issues.
• Work with the Verification team to ensure the block is fully validated.
• Mentor new college grads and interns to develop leadership skills.

Skills

Verilog/SystemVerilog

Digital design

Networking/Computer Architecture

Problem solving

Python/Perl

Mentoring

AI tools

Education

Bachelor's in Electrical Engineering

Master's degree preferred

Tools

EDA tools

Job description

Hewlett Packard Enterprise in California seeks an experienced ASIC/SoC design engineer to develop high-speed networking chips. You will translate specifications into micro-architectures and implement RTL with Verilog/SystemVerilog, driving tight timing and power targets.

You will collaborate with Physical Design and Verification teams to ensure full validation and high-quality silicon. Leadership opportunities include mentoring interns and new grads within a fast-paced silicon group.