Senior ASIC PD Engineer (Hybrid) – Timing & Flow Lead

HITEC; Northern (KY); Hybrid; USD 147,000 - 279,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer to support the development of complex, high-performance integrated circuits. This role is hybrid, requiring ~2 days per week in an HPE office, and involves collaboration with cross-functional teams across design, DFT, and verification to deliver scalable ASIC designs.

You will perform timing analysis, floorplanning, partitioning, ECOs, and signoff, with exposure to industry-standard EDA tools and scripting for flow

Qualifications

• BS or MS in Electrical/Computer Engineering, Microelectronics or related field.
• 6–10 years in ASIC/VLSI or semiconductor design with physical-design timing closure experience.
• Strong background in digital logic, circuit design and architecture.

Responsibilities

• Perform static timing analysis for hierarchical designs and full-chip levels.
• Create and maintain timing constraints and budgets for designs and processes.
• Drive timing-closure for partition-level and full-chip designs.
• Analyze timing reports, identify critical paths, and implement fixes.
• Perform synthesis, netlist quality checks, and formal verification.
• Support partitioning, floorplanning, and physical-design implementation.
• Develop ECOs and improve design flow automation.
• Mentor engineers and promote physical-design-aware architecture.

Skills

Static timing analysis

Timing constraints

Synthesis and netlist quality analysis

Formal verification

Floorplanning

Chip partitioning

ECO implementation

Flow automation

Scripting (Perl/Python/Tcl)

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering, Microelectronics

Tools

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Formality

Cadence RTL Compiler/Genus/LEC

Job description

Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer to support the development of complex, high-performance integrated circuits. This role is hybrid, requiring ~2 days per week in an HPE office, and involves collaboration with cross-functional teams across design, DFT, and verification to deliver scalable ASIC designs.

You will perform timing analysis, floorplanning, partitioning, ECOs, and signoff, with exposure to industry-standard EDA tools and scripting for flow