Hybrid Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise; Fort Collins (CO); Hybrid; USD 147,000 - 279,000; Full time

Benefits offered by this job

Health benefits

Career development programs

Inclusive culture

Job summary

Hewlett Packard Enterprise seeks an experienced ASIC Physical Design Engineer to advance complex high-performance ICs. You will contribute to design quality, synthesis, timing closure, floorplanning, and signoff, collaborating with cross-functional teams to develop scalable, physically aware methodologies.

The role requires 6–10 years in ASIC/VLSI, strong EDA tool proficiency, and scripting abilities. Hybrid work with office presence two days per week is offered, with emphasis on independent and

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering, Computer Engineering, or related field.
• 6–10 years of experience in ASIC/VLSI or semiconductor design with physical design and timing closure.
• Strong understanding of digital logic, circuit design, computer architecture, VLSI principles, and ASIC physical design.
• Experience with industry-standard EDA tools: Synopsys/Cadence suites and scripting for flows.

Responsibilities

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create, validate, and maintain timing constraints and budgets for design and process requirements.
• Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing.
• Analyze timing reports, identify critical paths, and implement fixes for performance, power, and area.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage ECCs (engineering change orders) for design improvements.
• Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff.
• Partner with cross-functional teams to promote physical-design-aware architecture and implementation.
• Review design and project activities for compliance with ASIC technology, methodology, and development standards.
• Provide technical guidance and mentoring to less-experienced engineers.

Skills

Static timing analysis

Timing closure

Scripting (Python)

Debugging

Teamwork

English communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Cadence RTL Compiler

Genus

Job description

Hewlett Packard Enterprise seeks an experienced ASIC Physical Design Engineer to advance complex high-performance ICs. You will contribute to design quality, synthesis, timing closure, floorplanning, and signoff, collaborating with cross-functional teams to develop scalable, physically aware methodologies.

The role requires 6–10 years in ASIC/VLSI, strong EDA tool proficiency, and scripting abilities. Hybrid work with office presence two days per week is offered, with emphasis on independent and