Senior ASIC Design Engineer – High-Speed Networking

Hewlett Packard Enterprise Company; Roseville (CA); Hybrid; USD 159,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise Company in Roseville, CA is seeking a Sr. ASIC Design Engineer to join our silicon team on a hybrid schedule, averaging two days per week in the office.

You will drive end-to-end ASIC design from spec to netlist, collaborating across RTL, physical design, and verification teams. The role emphasizes high-performance networking chips, with opportunities to mentor new graduates and shape module architectures.

Qualifications

• Bachelor's degree in Electrical Engineering required (Master's strongly desired) with 5+ years of relevant experience.
• Strong analytical/problem solving skills.
• Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus.
• Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired.
• Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired.
• Excellent written and verbal communications skills are good to have.
• Knowledge of Perl/Python is a plus.
• Experience with AI agentic tools is a plus.

Responsibilities

• Start with a functional specification of a module and produce a detailed micro-architecture specification that meets power/area requirements.
• Implement the design using Verilog or System Verilog.
• Write functional coverage/SVA to help verification catch corner case bugs.
• Work with the Physical Design team for optimal floorplan and timing closure; identify and fix timing in RTL to meet the frequency target.
• Work with the Verification team to make sure your block is fully validated.
• Mentor/guidance to new college-grad engineers and interns.

Skills

Analytical skills

Verilog

SystemVerilog

Perl

Python

Communication skills

AI tools

Education

Bachelor's degree in Electrical Engineering

Master's degree

Tools

EDA tools

Job description

Hewlett Packard Enterprise Company in Roseville, CA is seeking a Sr. ASIC Design Engineer to join our silicon team on a hybrid schedule, averaging two days per week in the office.

You will drive end-to-end ASIC design from spec to netlist, collaborating across RTL, physical design, and verification teams. The role emphasizes high-performance networking chips, with opportunities to mentor new graduates and shape module architectures.