Sr. Staff ASIC Design Engineer

Advanced Micro Devices; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose, CA, is seeking a candidate to join the front-end design/integration team to deliver high-quality silicon and achieve first-pass silicon success. You will implement and verify DFT architectures and features, including scan insertion and ATPG pattern generation.

The ideal candidate will have strong communication and problem-solving skills, experience with DFT methodologies, and proficiency in Verilog RTL, scripting, and EDA tools.

Qualifications

• Understanding of Design-for-Test (DFT) methodologies.
• Experience with DFT verification tools and standards (IEEE 1500, JTAG 1149.x).
• Bachelor's or master's degree in a relevant engineering field.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• Verification of ATPG patterns using gate-level simulation
• Test coverage and test cost reduction analysis
• Post-silicon support to accelerate yield learning

Skills

DFT methodologies

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Mentor TestKompress

Synopsys TetraMAX/DFTMAX

VCS

Perl scripting

Shell scripting

Verilog RTL

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you're redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger- technology that moves the world forward. Join us and, together, we'll advance your career.

THE ROLE:

Join a team developing next-generation graphics and compute technologies at AMD. As part of the front-end design/integration team, you will work closely with the Architecture, IP Design, Physical Design, and Product Engineering teams to deliver high-quality silicon and achieve first-pass silicon success.

THE PERSON:

The successful candidate will work closely with senior silicon design engineers. The ideal candidate will be highly detail-oriented and possess strong communication and problem-solving skills.

KEY RESPONSIBILITIES:

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• Verification of ATPG patterns using gate-level simulation
• Test coverage and test cost reduction analysis
• Post-silicon support to ensure successful bring-up and accelerate yield learning

PREFERRED EXPERIENCE:

• Understanding of Design-for-Test (DFT) methodologies and DFT verification experience (e.g., IEEE 1500, JTAG 1149.x, Scan, Memory BIST, etc.)
• Experience with Mentor TestKompress and/or Synopsys TetraMAX/DFTMAX
• Experience with VCS simulation tools, Perl and Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field

LOCATION:

San Jose, CA (Hybrid)

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.