Senior ASIC DFT Engineer – Test, ATPG & Yield

Broadcom Inc.; Fort Collins (CO); On-site; USD 141,000 - 226,000; Full time

Benefits offered by this job

Medical and dental benefits

401(k) with company match

Equity grants / ESPP

Job summary

Broadcom Inc. is seeking an experienced DFT lead for its ASIC Product Division at the San Jose Development Center. The role covers end-to-end DFT activities from architecture to tape-out, including interaction with cross-functional teams and external customers.

The candidate will implement and verify DFT techniques across Scan, MBIST, TAP and LBIST, with exposure to IO and SerDes. Strong Verilog, memory BIST and boundary-scan skills are required for success.

Qualifications

• Bachelor's degree and 12+ years of related experience required.
• Strong DFT background including IO/Analog DFT, ATPG, Scan, BIST.
• Experience with Scan Insertion and scan compression tools (e.g., DFT Compiler, Mentor TestKompress).
• Verilog coding, testbench generation and simulation experience.
• Memory BIST insertion and verification on embedded memory (SRAM, CAM, eDRAM, ROM).
• Boundary scan verification and test vector generation; knowledge of IEEE1149.1/1149.6.

Responsibilities

• Lead DFT programs from chip-level specification to implementation and verification.
• Implement DFT features: Scan, MBIST, TAP, LBIST, IO, SerDes integration.
• Generate, verify and debug test vectors; support ATE bring-up and RMA.
• Collaborate with STA/DI engineers for test closure across designs.
• Automate DFT and test vector generation flows; interact with customers.

Skills

DFT basics

ATPG

Scan insertion

Verilog

Memory BIST

Boundary scan

Test vector gen

Debugging

Education

Bachelor's degree

Master's degree

Tools

TetraMax

Fastscan

DFT Compiler

Mentor TestKompress

Tessent SSN

Job description

Broadcom Inc. is seeking an experienced DFT lead for its ASIC Product Division at the San Jose Development Center. The role covers end-to-end DFT activities from architecture to tape-out, including interaction with cross-functional teams and external customers.

The candidate will implement and verify DFT techniques across Scan, MBIST, TAP and LBIST, with exposure to IO and SerDes. Strong Verilog, memory BIST and boundary-scan skills are required for success.