Senior ASIC DFT/DV Engineer — Hybrid (San Jose/Austin)

Cisco Systems; Austin (TX); Hybrid; USD 168,000 - 245,000; Full time

Job summary

Cisco is seeking an experienced hardware DFT Engineer to design and validate test architectures for AI-era silicon platforms. You will shape DFT strategies, develop test benches using SystemVerilog, and work across design, verification, and PD teams to enable end-to-end silicon validation.

You will craft robust solutions, debug efficiently, and contribute to reusable test methodologies for new silicon device models, including bare die and stacked die configurations.

Qualifications

• Bachelor’s in Electrical Engineering or equivalent with 7+ years (or Master’s with 4+ years).
• Experience in test planning based on complex design specifications.
• Experience in testbench development using SystemVerilog.
• Experience debugging using DVE/Verdi.
• Experience with TCL, Python or Perl.

Responsibilities

• Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design.
• Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
• The job requires the candidate to have the ability to craft solutions and debug efficiently.

Skills

Test planning

Test bench

SystemVerilog

DVE Verdi

TCL

Python

Perl

Education

Bachelor's in Electrical Engineering

Master's degree

Tools

JTAG protocol

MBIST

Boundary scan

Job description

Cisco is seeking an experienced hardware DFT Engineer to design and validate test architectures for AI-era silicon platforms. You will shape DFT strategies, develop test benches using SystemVerilog, and work across design, verification, and PD teams to enable end-to-end silicon validation.

You will craft robust solutions, debug efficiently, and contribute to reusable test methodologies for new silicon device models, including bare die and stacked die configurations.