Senior Analog & Mixed-Signal Modeling Engineer

Us Tech Solutions; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Us Tech Solutions in Austin, TX, is seeking a seasoned engineer to build behavioral models of analog and mixed-signal circuits in SystemVerilog, integrating into a UVM verification environment for high-speed SerDes and SoC IP.

You will collaborate with analog and RTL teams, define model architecture and accuracy targets, and validate against transistor‑level results, while debugging simulations and documenting interfaces in a fast-paced CMOS process setting.

Qualifications

• Reading schematics, netlists and circuit specifications to define model scope.
• Developing architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Documenting model behavior, limitations and interfaces.

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Debugging simulation failures and finding the root cause in the model, RTL or testbench.
• Documenting model behavior, limitations and interfaces.

Skills

SystemVerilog

UVM methodology

Analog design and modeling

RTL coding

Debugging simulations

Waveform analysis

Education

Under-graduate degree preferred

Tools

VCS

LTSPICE

HSPICE

Job description

Us Tech Solutions in Austin, TX, is seeking a seasoned engineer to build behavioral models of analog and mixed-signal circuits in SystemVerilog, integrating into a UVM verification environment for high-speed SerDes and SoC IP.

You will collaborate with analog and RTL teams, define model architecture and accuracy targets, and validate against transistor‑level results, while debugging simulations and documenting interfaces in a fast-paced CMOS process setting.