Senior Analog & Mixed-Signal Verification Engineer

TetraMem - Accelerate The World; San Jose (CA); On-site; USD 110,000 - 300,000; Full time

Job summary

TetraMem - Accelerate The World is seeking an experienced mixed-signal verification engineer in San Jose, CA, to develop verification plans and testbenches for complex IC designs. You will verify analog/mixed-signal circuits, run simulations, and analyze results to ensure performance and reliability.

You will collaborate with circuit design and layout teams, write robust SystemVerilog models, and help optimize verification methodologies for scalable, portable flows.

Qualifications

• Bachelor's degree in Electrical Engineering with 5+ years of relevant industry experience or equivalent.
• Strong understanding of analog and mixed-signal circuit design and verification principles.
• Ability to write test plans, present results, and communicate clearly with multi-functional teams.
• Have familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, simulation time optimization, and coverage collection.
• Familiarity with analog behavioral models is a plus.

Responsibilities

• Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications.
• Design and develop verification testbenches using industry-standard verification languages and methodologies.
• Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability.
• Review and analyze verification results, and provide feedback to design teams.
• Collaborate with design and layout teams to identify and resolve design issues.
• Develop new verification methodologies, tools, and techniques, ensuring scalability and portability.
• Sign-off mixed signal designs in preparation for tapeout.
• Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL.

Skills

Verilog/SystemVerilog

Analog IC design

Mixed-signal verification

Python/Perl/C

Debugging skills

Teamwork

Education

Bachelor's degree in Electrical Engineering

Tools

Verilog simulators

SPICE simulators

Waveform viewers

Python scripting

Job description

TetraMem - Accelerate The World is seeking an experienced mixed-signal verification engineer in San Jose, CA, to develop verification plans and testbenches for complex IC designs. You will verify analog/mixed-signal circuits, run simulations, and analyze results to ensure performance and reliability.

You will collaborate with circuit design and layout teams, write robust SystemVerilog models, and help optimize verification methodologies for scalable, portable flows.