ASIC/RTL Design Engineer

VIVA; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

VIVA is seeking a modeling engineer in San Jose to build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX) in SystemVerilog that drop into a UVM verification environment for high-speed SerDes and SoC IP.

You will work with analog designers, RTL teams and verification engineers to deliver accurate models, balance fidelity with simulation speed, and validate against transistor-level results.

Qualifications

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology.
• Familiarity with high-speed interface standards is a plus.

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Debugging simulation failures and finding the root cause in the model, RTL or testbench.
• Documenting model behavior, limitations and interfaces.

Skills

SystemVerilog

UVM

Analog/mixed-signal fundamentals

Debugging simulations

RTL coding experience

Tools

VCS

LTSPICE

HSPICE

Job description

Fully onsite in San Jose CA

JOB DUTIES:

You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog. Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. You will work closely with analog circuit designers, RTL designers and verification engineers. Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

Our modeling engineers are expected to contribute in all of the following areas:

• Reading schematics, netlists and circuit specifications to define what each model must capture
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral SystemVerilog models of analog blocks
• Validating models against transistor-level simulation results
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces

EXPERIENCE AND EDUCATION:

Hands-on experience writing behavioral models of analog circuits in SystemVerilog. Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus.

Notes:

• Looking for a candidate with RTL coding experience but also Analog Design/Modeling experience.
• Would like to see experience with VCS and LTSPICE and HSPICE simulation.

VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status