ASIC & RTL/Analog Modeling Engineer (Onsite San Jose)

VIVA USA Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

VIVA is seeking a modeling engineer in San Jose to build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX) in SystemVerilog that drop into a UVM verification environment for high-speed SerDes and SoC IP.

You will work with analog designers, RTL teams and verification engineers to deliver accurate models, balance fidelity with simulation speed, and validate against transistor-level results.

Qualifications

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology.
• Familiarity with high-speed interface standards is a plus.

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Debugging simulation failures and finding the root cause in the model, RTL or testbench.
• Documenting model behavior, limitations and interfaces.

Skills

SystemVerilog

UVM

Analog/mixed-signal fundamentals

Debugging simulations

RTL coding experience

Tools

VCS

LTSPICE

HSPICE

Job description

VIVA is seeking a modeling engineer in San Jose to build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX) in SystemVerilog that drop into a UVM verification environment for high-speed SerDes and SoC IP.

You will work with analog designers, RTL teams and verification engineers to deliver accurate models, balance fidelity with simulation speed, and validate against transistor-level results.