Analog Design Engineer 5- #26-27291

US Tech Solutions; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Us Tech Solutions in Austin, TX, is seeking a seasoned engineer to build behavioral models of analog and mixed-signal circuits in SystemVerilog, integrating into a UVM verification environment for high-speed SerDes and SoC IP.

You will collaborate with analog and RTL teams, define model architecture and accuracy targets, and validate against transistor‑level results, while debugging simulations and documenting interfaces in a fast-paced CMOS process setting.

Qualifications

• Reading schematics, netlists and circuit specifications to define model scope.
• Developing architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Documenting model behavior, limitations and interfaces.

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Debugging simulation failures and finding the root cause in the model, RTL or testbench.
• Documenting model behavior, limitations and interfaces.

Skills

SystemVerilog

UVM methodology

Analog design and modeling

RTL coding

Debugging simulations

Waveform analysis

Education

Under-graduate degree preferred

Tools

VCS

LTSPICE

HSPICE

Job description

Duration: 12 months

Job Description

• You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.
• Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP.
• You will work closely with analog circuit designers, RTL designers and verification engineers.
• Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral SystemVerilog models of analog blocks
• Validating models against transistor-level simulation results
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces.

Experience

• Minimum 5 years' of experience

Skillsets

• Experience with RTL coding experience but also Analog Design/Modeling experience.
• Experience with VCS and LTSPICE and HSPICE simulation.
• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.

Education

• Under-graduate degree preferred.

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.