Analog Design Engineer 5- #26-27291

US Tech Solutions; San Jose (CA); Vor Ort; USD 140.000 - 180.000; Vollzeit

Zusammenfassung

US Tech Solutions seeks a candidate to build behavioral models of analog and mixed-signal circuits in SystemVerilog for a high-speed SerDes and SoC IP verification environment. You will collaborate with analog, RTL, and verification teams to deliver accurate models in advanced CMOS processes.

Responsibilities include reading specifications, designing architectures, coding SV models, validating against transistor data, and debugging complex simulation issues. Undergraduate degree preferred.

Qualifikationen

• :

Aufgaben

• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral SystemVerilog models of analog blocks
• Validating models against transistor-level simulation results
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces.

Kenntnisse

SystemVerilog

RTL coding

Analog design

UVM methodology

High-speed interfaces

Ausbildung

Under-graduate degree

Tools

VCS

LTSPICE

HSPICE

Jobbeschreibung

Duration: 12 months

Job Description

• You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.
• Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP.
• You will work closely with analog circuit designers, RTL designers and verification engineers.
• Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral SystemVerilog models of analog blocks
• Validating models against transistor-level simulation results
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces.

Experience

• Minimum 5 years' of experience

Skillsets

• Experience with RTL coding experience but also Analog Design/Modeling experience.
• Experience with VCS and LTSPICE and HSPICE simulation.
• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.

Education

• Under-graduate degree preferred.

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.