Mixed-Signal Behavioral Modeling Engineer

Mogi I/O : OTT/Podcast/Short Video Apps for you; Dallas (TX); On-site; USD 90,000 - 120,000; Full time

Job summary

A semiconductor innovator is seeking a Mixed-Signal Behavioral Modeling Engineer to perform verification and modeling of advanced DSP chips. Responsibilities include developing behavioral models for analog designs, running verification, and collaborating with design teams. The ideal candidate has robust experience in behavioral modeling and mixed-signal verification, primarily using Verilog/SystemVerilog. This is a full-time, onsite role located in Austin, Texas.

Qualifications

• 5+ years of mixed-signal verification experience.
• Strong background in Behavioral Modelling for analog-to-digital verification.
• Hands-on Verilog/SystemVerilog verification coding.

Responsibilities

• Perform behavioral modeling of analog designs.
• Conduct mixed-signal dynamic verification using chip-level digital design tools.
• Develop test plans and verification strategies.

Skills

Behavioral Modelling

Verilog/SystemVerilog coding

Mixed-signal verification

Communication skills

Communication skills

Tools

Cadence Virtuoso

Synopsys verification tools

Cadence verification tools

Job description

Mixed‑Signal Behavioral Modeling Engineer

Full‑time, Onsite (Austin, Texas). 5+ years of experience. Employment Type: Direct Hire (Core Team). Sponsorship: Likely H1B/EAD eligible.

Our client is a Series‑D semiconductor innovator specializing in programmable coherent DSP solutions powering cloud and AI infrastructure. Their breakthrough DSP technology is foundational to high‑speed data center interconnects, enabling faster, more efficient cloud and AI communications.

Job Overview

The role focuses on mixed‑signal verification for advanced DSP‑based communication and AI interconnect chips. You’ll develop behavioral models for analog blocks, run mixed‑signal dynamic verification, and collaborate with world‑class analog and digital design teams to validate next‑gen coherent DSP solutions.

Key Responsibilities

• Perform behavioral modeling (BM) of analog designs to enable digital verification.
• Conduct mixed‑signal dynamic verification (without AMS) using chip‑level digital design tools.
• Write, simulate, and debug Verilog/SystemVerilog verification code.
• Use Cadence Virtuoso Schematics to interface with analog designs.
• Develop test plans, verification strategies, and scalable testbench automation.
• Collaborate with DSP, analog, and digital engineering teams to validate high‑speed designs.
• Present verification results, maintain coverage metrics, and ensure first‑pass success in silicon.

Minimum Qualifications

• 5+ years of mixed‑signal verification experience.
• Strong background in Behavioral Modelling (BM) for analog‑to‑digital verification.
• Hands‑on Verilog/SystemVerilog verification coding.
• Familiarity with Virtuoso Schematics.
• Basic understanding of analog design fundamentals.

Preferred Qualifications

• Experience with UVM (Universal Verification Methodology).
• Background working with both Synopsys and Cadence verification tools.
• Understanding of advanced verification infrastructure – simulators, waveform viewers, coverage, execution automation.
• Proven track record of building portable/scalable test environments.
• Strong communication skills; ability to write test plans, document results, present to multi‑functional teams.

Seniority Level

Entry level.