Lead Analog & Mixed-Signal Modeling Engineer (SystemVerilog)

Us Tech Solutions; San Jose (CA); On-site; USD 140,000 - 180,000; Full time

Job summary

US Tech Solutions seeks a candidate to build behavioral models of analog and mixed-signal circuits in SystemVerilog for a high-speed SerDes and SoC IP verification environment. You will collaborate with analog, RTL, and verification teams to deliver accurate models in advanced CMOS processes.

Responsibilities include reading specifications, designing architectures, coding SV models, validating against transistor data, and debugging complex simulation issues. Undergraduate degree preferred.

Qualifications

• :

Responsibilities

• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral SystemVerilog models of analog blocks
• Validating models against transistor-level simulation results
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces.

Skills

SystemVerilog

RTL coding

Analog design

UVM methodology

High-speed interfaces

Education

Under-graduate degree

Tools

VCS

LTSPICE

HSPICE

Job description

US Tech Solutions seeks a candidate to build behavioral models of analog and mixed-signal circuits in SystemVerilog for a high-speed SerDes and SoC IP verification environment. You will collaborate with analog, RTL, and verification teams to deliver accurate models in advanced CMOS processes.

Responsibilities include reading specifications, designing architectures, coding SV models, validating against transistor data, and debugging complex simulation issues. Undergraduate degree preferred.