Senior Analog/Mixed-Signal Verilog Modeling Engineer

Broadcom Inc.; Irvine (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays

Paid sick leave and vacation time

Paid Family Leave

Job summary

Broadcom Inc. in Irvine seeks an experienced DMS model developer to create Digital‑Mixed Signal models for analog IPs using SystemVerilog. You will interface with analog design and DV teams to support verification, and leverage Verilog‑AMS for modeling and Cadence tools for linting and simulation.

The role requires a strong background in RTL/DTL coding, testbench creation, and hands‑on scripting (TCL/Perl/Python) with exposure to AI-assisted modeling approaches.

Qualifications

• Bachelor's degree and 8+ years of related experience.
• Develop Digital-Mixed Signal models for analog IPs using SystemVerilog.
• Familiar with Verilog-AMS modeling language and Cadence linting/simulation tools.

Responsibilities

• Develop DMS models for touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs.
• Interface with analog design and chip DV teams to support verification.
• Create testbenches and run RTL vs schematic verification; maintain documentation.

Skills

SystemVerilog

Verilog-AMS

UDT/UDR

Scripting: TCL/Perl/Python

Cadence tools

Analog modeling

Education

Bachelor's degree

Tools

Cadence ncsim

xrun

VCS

Cursor

chipAgents

Job description

Broadcom Inc. in Irvine seeks an experienced DMS model developer to create Digital‑Mixed Signal models for analog IPs using SystemVerilog. You will interface with analog design and DV teams to support verification, and leverage Verilog‑AMS for modeling and Cadence tools for linting and simulation.

The role requires a strong background in RTL/DTL coding, testbench creation, and hands‑on scripting (TCL/Perl/Python) with exposure to AI-assisted modeling approaches.