Senior Analog Behavior Modeling Engineer

MediaTek; Austin (TX); On-site; USD 128,600 - 217,200; Full time

Benefits offered by this job

Health insurance

401K

Paid holidays

PTO

Parental leave

Job summary

MediaTek Austin is seeking an experienced Analog Behavior Modeling Engineer to join our mixed-signal design team. You will develop behavioral models in SystemVerilog for analog blocks such as LDOs, bandgaps, and temperature sensors, enabling efficient design verification and seamless integration with digital verification environments.

You will verify models against specifications, perform MvS verification, and implement assertions.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of experience in analog/mixed-signal verification or behavioral modeling.
• Strong knowledge of SystemVerilog & RNM.
• Understanding of analog circuits like bandgaps, LDOs, oscillators, ADCs/DACs.
• Experience with simulation and debug tools like Synopsys VCS/Verdi.
• Proficiency in scripting languages like Python.
• Excellent communication skills to work across analog design, digital design, and verification teams.

Responsibilities

• Develop behavioral models in SystemVerilog for analog blocks including ring oscillators, reference voltage generators, voltage/frequency meters, LDOs, and temperature sensors.
• Perform unit level verification to verify behavioral model against analog design specification.
• Perform Model vs. Schematic (MvS) verification to ensure model correctness and achieve comprehensive coverage metrics.
• Debug and resolve analog behavioral modeling issues encountered in system-level digital simulations.
• Develop SystemVerilog assertions within models to verify that digital controllers meet analog specification requirements.

Skills

SystemVerilog

RNM (Real Number Modeling)

Analog/mixed-signal verification

Python scripting

VCS/Verdi debugging

Communication skills

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Synopsys VCS/Verdi

Job description

MediaTek Austin is seeking an experienced Analog Behavior Modeling Engineer to join our mixed-signal design team. You will develop behavioral models in SystemVerilog for analog blocks such as LDOs, bandgaps, and temperature sensors, enabling efficient design verification and seamless integration with digital verification environments.

You will verify models against specifications, perform MvS verification, and implement assertions.