RTL Digital Design Intern — Hybrid (DDR6 AI Memory)

Rambus; Johns Creek (GA); Hybrid; USD 34,000 - 55,000; Full time

Benefits offered by this job

Gym membership

Medical benefits

Job summary

Rambus in Johns Creek, Georgia seeks an RTL Digital Design Intern to join the Memory Interface Chip BU. You will develop Verilog/SystemVerilog RTL for DDR5/DDR6 memory interfaces and work with senior engineers on silicon projects for AI data centers.

The role reports to the Digital Design Director and involves collaborating with verification teams to bring up silicon, with a hybrid on-site/remote schedule. Strong RTL and scripting skills are required.

Qualifications

• BS or MS in Electrical Engineering or Computer Engineering.
• Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms.
• Background in digital RTL design including LEC, CDC, Lint, DFT, BIST, and STA tools.
• High aptitude with Verilog and SystemVerilog.
• Ability to document design techniques, test, and verification methodologies.
• Python/Perl script development.
• Strong debugging, analytical, and communication skills.

Responsibilities

• Develop Verilog/SystemVerilog RTL for DDR5/DDR6 memory interface products.
• Design digital control logic, state machines, and register interfaces.
• Analyze and optimize RTL designs for power, performance, and area (PPA).
• Support timing closure and STA.
• Create behavioral models for simulation and verification.
• Work with verification and validation teams during silicon bring-up and debugging.

Skills

Verilog

SystemVerilog

RTL design

Python/Perl

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

STA tools

DFT

Job description

Rambus in Johns Creek, Georgia seeks an RTL Digital Design Intern to join the Memory Interface Chip BU. You will develop Verilog/SystemVerilog RTL for DDR5/DDR6 memory interfaces and work with senior engineers on silicon projects for AI data centers.

The role reports to the Digital Design Director and involves collaborating with verification teams to bring up silicon, with a hybrid on-site/remote schedule. Strong RTL and scripting skills are required.