Sr. SI/PI Engineer — DDR Memory Interfaces (Hybrid)

Rambus

Morrisville (NC)

Hybrid

USD 126,000 - 234,000

Full time

5 days ago
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Benefits offered by this job

Base salary
Bonus
Equity
Medical benefits
Gym membership

Job summary

Rambus is seeking a Sr. Principal Engineer with signal integrity and package design expertise to join the Memory Interface Chips BU in Georgia.

You will model, analyze, and simulate SI/PI for DDR4/5 devices with speeds up to 16000+ MT/s, reporting to the Senior Director. This full-time, hybrid role requires leading SI/PI methodologies, guiding packaging and PCB decoupling, and collaborating with design, validation, and customers to deliver high‑quality memory interfaces.

Qualifications

  • MS or PhD in Electrical Engineering with 10+ years of industry experience in SI/PI and packaging.
  • Experience with DDR4/5 memory interfaces and SERDES is required.
  • Strong background in EM and transmission line theory; proficient in SI techniques.

Responsibilities

  • Create SI/PI methodologies and work with Design and SI teams on package design.
  • Define specifications for packaging, PCB routing, decoupling, and channel simulations.
  • Provide guidance based on SI/PI studies to achieve superior SI performance.
  • Collaborate with customers to develop optimum SI/PI solutions.
  • Assist in lab bring-up and debugging as needed.

Skills

Signal integrity
Package design
DDR4/5
Spice/ADS simulations
Lab correlation
SI/PI methodologies

Education

MS or PhD in Electrical Engineering

Tools

ADS
HFSS
Q3D/PowerSI
Virtuoso
RedHawk/Totem

Job description

Rambus is seeking a Sr. Principal Engineer with signal integrity and package design expertise to join the Memory Interface Chips BU in Georgia.

You will model, analyze, and simulate SI/PI for DDR4/5 devices with speeds up to 16000+ MT/s, reporting to the Senior Director. This full-time, hybrid role requires leading SI/PI methodologies, guiding packaging and PCB decoupling, and collaborating with design, validation, and customers to deliver high‑quality memory interfaces.

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