Hybrid Principal Memory Controller RTL Design Engineer

Rambus; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Job summary

Rambus in Hillsboro, Oregon seeks a Principal Logic Design Engineer to shape micro-architecture and RTL for next‑gen memory controllers for data centers and AI. You will drive PPA-driven design decisions and collaborate across verification, physical design, and customer engagements.

The role requires deep SystemVerilog/Verilog expertise, 10+ years of ASIC/FPGA experience, and a track record in complex memory interfaces. Hybrid work offers onsite and remote flexibility.

Qualifications

• Strong SystemVerilog/Verilog RTL design expertise.
• Questa/Incisive/VCS simulator experience.
• Python/Perl/TCL scripting experience.
• Ability to learn quickly and work independently.
• Solid communication and project management skills.
• 10+ years of logic design experience (ASIC/FPGA) with BS EE, or 8+ years with MS EE.

Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces.
• Analyze performance, power, and area trade-offs and drive design decisions based on quantitative data.
• Collaborate closely with verification team to shape test plans and improve verification coverage.
• Work with physical design team to understand and resolve timing, power, and congestion challenges.
• Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary.
• Provide technical support to FAE team on pre-sales customer engagements.
• Provide technical support to AE team on post-sale customer deliveries.

Skills

SystemVerilog RTL design

Simulation tools

Scripting (Python/Perl/TCL)

Independent learner

Communication & PM

ASIC/FPGA design experience

Education

Bachelor of Science in Electrical Engineering

Master of Science in Electrical Engineering

Tools

Questa/Incisive/VCS simulators

Job description

Rambus in Hillsboro, Oregon seeks a Principal Logic Design Engineer to shape micro-architecture and RTL for next‑gen memory controllers for data centers and AI. You will drive PPA-driven design decisions and collaborate across verification, physical design, and customer engagements.

The role requires deep SystemVerilog/Verilog expertise, 10+ years of ASIC/FPGA experience, and a track record in complex memory interfaces. Hybrid work offers onsite and remote flexibility.