Senior Analog/Mixed-Signal Design Engineer (DDR/High-Speed)

Rambus.com; Johns Creek (GA); Hybrid; USD 169,000 - 254,000; Full time

Benefits offered by this job

Gym membership

Equity/Stock options

Matching 401(k)

Comprehensive medical and dental

Time-off program

Job summary

Rambus Memory Interface Chips BU is seeking a seasoned engineer to lead analog and mixed-signal design for high-speed memory interfaces. You will architect, simulate, and validate receiver, samplers, and signal conditioning circuits, while coordinating with global teams to ensure timely, high-quality results.

Ideal candidates hold an MSEE/Ph.D. with 10+ years in analog/mixed-signal design, with DDR interface experience and Verilog knowledge considered strong assets.

Qualifications

• MSEE/Ph.D. with 10+ years of analog/mixed-signal circuit design experience.
• Must have understanding of SI/PI principles and interaction with receiver front-end principles.
• Direct chip design experience in DDR interface design is a strong plus.
• Experience with Verilog coding is a strong plus.

Responsibilities

• Owner and domain expert of analog and mixed signal designs at chip and block level, especially for high-speed data receivers.
• Architect, design, simulate and characterize high-performance and low-power high-speed circuits including receiver, samplers, and signal conditioning circuits.
• Modeling of chip and block level at various levels of detail for design tradeoff analysis and voltage and timing budgeting.
• Supervise analog layout engineering to ensure attention to detail on high performance analog layout for critical IO blocks.
• Work closely with cross-functional teams across different geographies and time zones to ensure engagement and execution.
• Other responsibilities include layout supervision, design documentation, guiding and debugging post-silicon validation, correlating silicon to simulation.

Skills

DDR interface design

Verilog coding

SI/PI principles

Receiver front-end principles

Education

MSEE/Ph.D. with 10+ years analog/mixed-signal circuit design experience

Job description

Rambus Memory Interface Chips BU is seeking a seasoned engineer to lead analog and mixed-signal design for high-speed memory interfaces. You will architect, simulate, and validate receiver, samplers, and signal conditioning circuits, while coordinating with global teams to ensure timely, high-quality results.

Ideal candidates hold an MSEE/Ph.D. with 10+ years in analog/mixed-signal design, with DDR interface experience and Verilog knowledge considered strong assets.