AI-Driven RTL Design Engineer for Production Silicon

Voltai; Palo Alto (CA); In loco; USD 150.000 - 230.000; Tempo pieno

Descrizione del lavoro

Voltai, a California-based company, seeks an experienced RTL design engineer to own microarchitecture and RTL for production silicon. You will drive the design flow from microarchitecture to signoff-ready code and collaborate with top semiconductor partners.

You’ll debug timing, run lint and CDC, and review AI-generated RTL to set the standard for high-quality design. You’ll interface with verification, backend teams, and customer design teams when needed.

Competenze

• 5+ years of RTL design experience on chips that taped out.
• Expert SystemVerilog/Verilog and strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.

Mansioni

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
• Work directly with customer design teams when needed.

Conoscenze

RTL design

SystemVerilog

Python scripting

Tcl scripting

Timing closure

PCIe or AXI

Strumenti

lint

CDC

synthesis

timing analysis

Descrizione del lavoro

Voltai, a California-based company, seeks an experienced RTL design engineer to own microarchitecture and RTL for production silicon. You will drive the design flow from microarchitecture to signoff-ready code and collaborate with top semiconductor partners.

You’ll debug timing, run lint and CDC, and review AI-generated RTL to set the standard for high-quality design. You’ll interface with verification, backend teams, and customer design teams when needed.