RTL Design Engineer — Tapeout-Ready AI ASICs

Normal Computing Corp.; New York (NY); On-site; USD 120,000 - 160,000; Full time

Job summary

Normal Computing is seeking an RTL Design Engineer to design and verify the digital logic at the heart of its thermodynamic hardware. You will own RTL from microarchitecture to tapeout, writing synthesizable SystemVerilog and building verification environments with UVM, cocotb, or formal tools.

You will work closely with architects and physical designers to ensure correctness and realizability. This role blends design and verification, demanding silicon experience and a track record of tapeouts.

Qualifications

• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place‑and‑route.
• Experience authoring verification environments (UVM, cocotb, formal) or equivalent.
• At least one tapeout in background from any node or company size.
• Ability to work across design and verification without strict separation.

Responsibilities

• Write and own synthesizable RTL in SystemVerilog across datapath to memory interfaces.
• Author functional verification environments using UVM, cocotb, formal property checking.
• Translate high-level specs into implementable microarchitectures with architecture teams.
• Collaborate with physical design on timing, floorplanning, and DFT.
• Develop and maintain simulation infrastructure, regression pipelines, and coverage flows.
• Participate in design reviews and contribute to architecture decisions.
• Support tapeout preparation, integration, and post-silicon bring‑up.

Skills

SystemVerilog RTL

RTL verification

UVM

cocotb

Formal methods

Tools

Verificatio n tools

Job description

Normal Computing is seeking an RTL Design Engineer to design and verify the digital logic at the heart of its thermodynamic hardware. You will own RTL from microarchitecture to tapeout, writing synthesizable SystemVerilog and building verification environments with UVM, cocotb, or formal tools.

You will work closely with architects and physical designers to ensure correctness and realizability. This role blends design and verification, demanding silicon experience and a track record of tapeouts.