Lead RTL Design Engineer — Architect & Tapeout Lead

Normal Computing Corporation; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Job summary

Normal Computing seeks a Lead RTL Design Engineer to own the RTL from microarchitecture to tapeout and to drive the design team's execution. You will craft synthesizable SystemVerilog and work with verification engineers to validate the design against formal and conventional methods.

As a lead, you will shape architecture, guide the methodology, and align with architects and physical designers to meet timing and area constraints in a fast-moving environment.

Qualifications

• Experience leading an RTL design team through multiple tapeouts.
• Hands-on SystemVerilog RTL development and closure through synthesis.
• Experience with datapaths, pipelines, or microarchitectures not fully specified upfront.
• Strong debugging across simulations, waveforms, and formal methods.
• Ability to work with architects and physical designers.

Responsibilities

• Lead RTL design from microarchitecture to tapeout and bring-up.
• Define and enforce RTL coding standards and ensure synthesizable RTL.
• Translate high-level specs into implementable microarchitectures with architecture.
• Coordinate with verification to review plans and close coverage.
• Collaborate with physical design for timing, floorplanning, and DFT.
• Participate in design reviews and drive architecture decisions.

Job description

Normal Computing seeks a Lead RTL Design Engineer to own the RTL from microarchitecture to tapeout and to drive the design team's execution. You will craft synthesizable SystemVerilog and work with verification engineers to validate the design against formal and conventional methods.

As a lead, you will shape architecture, guide the methodology, and align with architects and physical designers to meet timing and area constraints in a fast-moving environment.