Senior RTL Design Lead for Tapeout & Architecture

Normal Computing Corp.; Mountain View (CA); On-site; USD 190,000 - 230,000; Full time

Job summary

Normal Computing seeks a Lead RTL Design Engineer to lead the digital logic core of its thermodynamic hardware. You will drive RTL from microarchitecture to tapeout, writing synthesizable SystemVerilog and coordinating with verification and physical design to meet area and timing constraints.

The role emphasizes leadership, design methodology, and cross-functional collaboration with architecture, verification, and physical design teams, guiding tapeout sign-off and post-silicon bring-up in a

Qualifications

• Experience leading an RTL design team through multiple tapeouts.
• Hands-on production RTL in SystemVerilog and closing it through synthesis and place-and-route.
• Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
• Strong debugging instincts across simulation, waveforms, and formal counterexamples.

Responsibilities

• Team Leadership: organize and set the standard and high expectations for the RTL design team.
• RTL Design: write and own synthesizable RTL in SystemVerilog across datapath to control and memory interfaces.
• Microarchitecture: translate high-level specifications into implementable microarchitectures.
• Verification: review plans, assist on debug, and close coverage with verification team.
• Physical Design Collaboration: timing closure, PPA optimization, floorplanning constraints, and DFT.
• Design Reviews: participate in reviews and contribute to architecture decisions.
• Tapeout & Bring-up: support tapeout readiness and post-silicon bring-up as needed.

Skills

RTL design leadership

SystemVerilog

Tapeout experience

Debugging

Architect collaboration

Tools

EDA tooling

Job description

Normal Computing seeks a Lead RTL Design Engineer to lead the digital logic core of its thermodynamic hardware. You will drive RTL from microarchitecture to tapeout, writing synthesizable SystemVerilog and coordinating with verification and physical design to meet area and timing constraints.

The role emphasizes leadership, design methodology, and cross-functional collaboration with architecture, verification, and physical design teams, guiding tapeout sign-off and post-silicon bring-up in a