RTL Design Micro-Architect for AI Accelerators (Remote)

Acceler8 Talent; Mountain View (CA); Remote; USD 140,000 - 210,000; Full time

Job summary

Acceler8 Talent is assisting a fast-growing AI hardware company with a Mountain View, CA or Remote location to hire experienced silicon micro-architects and RTL designers. The role covers architecture to RTL implementation for high-performance accelerators and requires strong collaboration with verification, DFT, physical design, and software teams.

Responsibilities include design ownership from microarchitecture through sign-off, driving milestones like design freeze and tapeout, and optimizing

Qualifications

• 4+ years of experience with SystemVerilog and RTL-development workflows.

Responsibilities

• Contribute to scalable silicon architecture-to-design methodologies spanning blocks, subsystems, and full-chip development.
• Own entire subsystems, major blocks, or chip-level deliverables from microarchitecture through sign-off-ready RTL.
• Define and review microarchitecture and design specifications.
• Drive execution toward major silicon milestones including design freeze and tapeout.
• Track and optimize performance, power, area, timing, and design-quality goals.
• Partner closely with verification, DFT, and physical-design engineers throughout the development lifecycle.
• Drive timing and area closure while maintaining functional correctness and design quality.
• Develop production-quality RTL for high-performance compute and accelerator architectures.

Skills

SystemVerilog

RTL development

Python

C/C++

ASIC design

SoC design

Job description

Acceler8 Talent is assisting a fast-growing AI hardware company with a Mountain View, CA or Remote location to hire experienced silicon micro-architects and RTL designers. The role covers architecture to RTL implementation for high-performance accelerators and requires strong collaboration with verification, DFT, physical design, and software teams.

Responsibilities include design ownership from microarchitecture through sign-off, driving milestones like design freeze and tapeout, and optimizing