Senior Digital Design Engineer, SoC RTL & Tapeout

Unconventional, Inc.; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Meals in Palo Alto office

Job summary

Unconventional, Inc. is seeking a Member of Technical Staff, Digital Design Engineer, to join a small, multi-disciplinary R&D team in California.

You will own RTL design, drive tapeout-ready blocks, and integrate third-party IP into the novel SoC fabric at the intersection of AI, physics, and computer architecture. The role requires 8+ years in digital ASIC/SoC design, strong Verilog RTL skills, and leadership ability to mentor juniors.

Qualifications

• Bachelor's or Master’s degree in Electrical/Electronic Engineering or related field.
• 8+ years of industry experience in digital ASIC/SoC design.
• Strong Verilog RTL coding and digital design fundamentals.
• Familiarity with standard EDA tools for simulation, synthesis, linting, and CDC analysis.

Responsibilities

• Lead digital block micro-architecture and top-level integration for CPU, memory subsystems, and interfaces.
• Mentor junior digital design engineers and establish best practices.
• Drive hands-on RTL design and ensure PPA targets are met.
• Perform synthesis, timing, linting, and CDC checks and support DV environment.

Skills

Verilog RTL

ASIC/SoC design

Leadership

Education

B.S./M.S. in EE

Tools

EDA tools

Job description

Unconventional, Inc. is seeking a Member of Technical Staff, Digital Design Engineer, to join a small, multi-disciplinary R&D team in California.

You will own RTL design, drive tapeout-ready blocks, and integrate third-party IP into the novel SoC fabric at the intersection of AI, physics, and computer architecture. The role requires 8+ years in digital ASIC/SoC design, strong Verilog RTL skills, and leadership ability to mentor juniors.