RTL Design Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A tech startup in Mountain View is looking for an experienced RTL Engineer to lead the top-level integration of complex SoCs. This role involves collaborating with various teams to ensure high-quality chip-level design and successful tapeouts. Ideal candidates will have expertise in SystemVerilog, strong integration experience, and the ability to handle diverse chip design concepts. This opportunity is crucial for advancing cutting-edge AI silicon production.

Qualifications

• Hands-on experience with top-level RTL integration of ASICs or SoCs.
• Strong skills in SystemVerilog for integration and debugging.
• Deep knowledge of chip-level design concepts.
• Experience with synthesis and sign-off flows.
• Proven track record of working across multi-disciplinary teams.

Responsibilities

• Own the top-level RTL integration of large, complex SoCs.
• Develop and maintain integration methodologies for scalable assembly.
• Drive chip-level reviews across milestones.
• Resolve integration issues with subsystem owners and verification teams.
• Deliver sign-off quality RTL suitable for synthesis and emulation.

Skills

Top-level RTL integration of ASICs or SoCs

SystemVerilog

Python

C/C++

Chip-level design concepts

Synthesis and sign-off flows

Job description

Acceler8 Talent is seeking an experienced RTL Engineer to join a record-breaking startup building a compute platform for AGI. This is a chance to own the full-chip RTL assembly process, collaborate across subsystems, and ensure the world’s most advanced AI silicon comes together into a seamless, production-ready product.

What you'll do:

• Own the top-level RTL integration of large, complex SoCs from subsystem drop to sign-off.
• Develop and maintain integration methodologies for scalable assembly across full-chip builds.
• Drive chip-level reviews of connectivity, functionality, timing, and PPA closure across milestones (integration freeze, design freeze, tapeout).
• Work closely with subsystem owners, verification, DFT, and physical design teams to resolve integration issues and ensure clean handoff to downstream flows.
• Debug and resolve top-level RTL issues (connectivity mismatches, CDC/RDC, resets, clocks, design lint) across the chip hierarchy.
• Deliver sign-off quality RTL suitable for synthesis, equivalence checking, and emulation.

Who you are:

• Hands-on experience with top-level RTL integration of ASICs or SoCs, from subsystem assembly through production silicon.
• Strong skills in SystemVerilog for integration and debugging; familiarity with Python, C/C++, or scripting languages to support integration flows.
• Deep knowledge of chip-level design concepts: clocks, resets, power domains, CDC/RDC, lint, connectivity, and hierarchical build flows.
• Experience with synthesis and sign-off flows (equivalence checking, lint, DFT/scan stitching, power/timing checks).
• Proven track record of working across multi-disciplinary teams (design, verification, physical design, DFT) to achieve high-quality tapeouts.
• Plus: familiarity with emulation platforms and methodologies.
• Plus: experience with silicon bring-up and debug.