RTL Design Engineer: AI-Driven Silicon & Microarchitecture

Voltai; United States; On-site; USD 140,000 - 190,000; Full time

Job summary

Voltai is seeking an experienced RTL design engineer to own microarchitecture and RTL implementation for production silicon. You will collaborate with backend and verification teams to drive timing closure and ensure high-quality designs.

You will review AI-generated RTL, work with customer design teams, and contribute to defining standards for correct design. 5+ years of SystemVerilog/Verilog experience required.

Qualifications

• 5+ years of RTL design experience on chips that taped out.
• Expert SystemVerilog/Verilog and strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.
• Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
• Python or Tcl scripting.

Responsibilities

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
• Work directly with customer design teams when needed.

Skills

SystemVerilog/Verilog

RTL design

lint

CDC

synthesis

timing closure

AXI

PCIe

Ethernet

DDR

Python scripting

Job description

Voltai is seeking an experienced RTL design engineer to own microarchitecture and RTL implementation for production silicon. You will collaborate with backend and verification teams to drive timing closure and ensure high-quality designs.

You will review AI-generated RTL, work with customer design teams, and contribute to defining standards for correct design. 5+ years of SystemVerilog/Verilog experience required.