RTL Designer

Acceler8 Talent; Mountain View (CA); Remote; USD 140,000 - 210,000; Full time

Job summary

Acceler8 Talent is assisting a fast-growing AI hardware company with a Mountain View, CA or Remote location to hire experienced silicon micro-architects and RTL designers. The role covers architecture to RTL implementation for high-performance accelerators and requires strong collaboration with verification, DFT, physical design, and software teams.

Responsibilities include design ownership from microarchitecture through sign-off, driving milestones like design freeze and tapeout, and optimizing

Qualifications

• 4+ years of experience with SystemVerilog and RTL-development workflows.

Responsibilities

• Contribute to scalable silicon architecture-to-design methodologies spanning blocks, subsystems, and full-chip development.
• Own entire subsystems, major blocks, or chip-level deliverables from microarchitecture through sign-off-ready RTL.
• Define and review microarchitecture and design specifications.
• Drive execution toward major silicon milestones including design freeze and tapeout.
• Track and optimize performance, power, area, timing, and design-quality goals.
• Partner closely with verification, DFT, and physical-design engineers throughout the development lifecycle.
• Drive timing and area closure while maintaining functional correctness and design quality.
• Develop production-quality RTL for high-performance compute and accelerator architectures.

Skills

SystemVerilog

RTL development

Python

C/C++

ASIC design

SoC design

Job description

Micro-Architect and RTL Designer

Location: Mountain View, CA or Remote

Employment Type: Full-time

About the Role

A fast-growing AI hardware company is building a vertically integrated compute platform spanning silicon, systems, and software for large-scale machine learning workloads.

The team is looking for experienced silicon micro-architects and RTL design engineers to develop high-performance accelerator silicon across compute, memory management, high-speed connectivity, and other critical subsystem areas.

Successful candidates will own significant portions of the design from architecture and microarchitecture through implementation and sign-off, working closely with verification, DFT, physical design, and software teams.

What You’ll Do

• Contribute to scalable silicon architecture-to-design methodologies spanning blocks, subsystems, and full-chip development.
• Own entire subsystems, major blocks, or chip-level design deliverables from microarchitecture through sign-off-ready RTL.
• Define and review microarchitecture and design specifications.
• Drive execution toward major silicon milestones including design freeze and tapeout.
• Track and optimize performance, power, area, timing, and design-quality goals.
• Partner closely with verification, DFT, and physical-design engineers throughout the development lifecycle.
• Drive timing and area closure while maintaining functional correctness and design quality.
• Develop production-quality RTL for high-performance compute and accelerator architectures.

What We’re Looking For

• Concept-to-silicon experience developing ASIC or SoC subsystems or top-level functionality from architecture specification through production silicon.
• 4+ years of experience with SystemVerilog and related RTL-development workflows.
• Experience with Python, C/C++, or similar scripting/programming languages used in chip-design environments.
• Production experience with silicon microarchitecture and RTL design for one or more of the following:
• CPUs
• GPUs
• AI/ML accelerators
• High-performance compute architectures
• Memory-management subsystems
• High-speed connectivity
• Experience testing designs and partnering closely with verification teams toward performance and coverage closure.
• Hands-on experience with synthesis, lint, and related RTL sign-off flows.
• Strong understanding of performance, power, and area tradeoffs in complex digital designs.

Nice to Have

• Verification or emulation experience.
• Familiarity with hardware emulation platforms and methodologies.
• High-speed I/O IP experience.
• Experience designing data-movement and storage logic such as:
• Caches
• Buffers
• Crossbars
• FIFOs
• Memory controllers
• Interconnects
• DMA engines
• NoCs
• Experience with compute pipelines, execution units, or accelerator datapaths.
• Experience with chip-level or subsystem timing closure.

Keywords

Microarchitecture, RTL Design, SystemVerilog, Verilog, ASIC, SoC, AI Accelerator, ML Accelerator, GPU, CPU, High-Performance Compute, HPC, Compute Architecture, Digital Design, Logic Design, Microarchitecture Design, RTL Microarchitecture, Synthesis, Lint, Timing Closure, PPA, Performance Power Area, Design Sign-Off, Tapeout, Cache, Memory Subsystem, Memory Management, Buffer, FIFO, Crossbar, Interconnect, NoC, Network-on-Chip, DMA, Datapath, Pipeline, Execution Unit, High-Speed I/O, DFT, Physical Design, Verification, Emulation, Python, C, C++.