Physical Design Engineer – ASIC/RTL2GDSII

SpaceX; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Medical coverage

Vision coverage

Dental coverage

401(k)

Paid vacation

Paid holidays

Disability insurance

Life insurance

Parental leave

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to design and implement next‑gen ASICs for Starlink. You will work with cross‑disciplinary teams to push performance, power, and area targets for space and ground infrastructure.

The role emphasizes hands‑on RTL2GDSII flows, scripting automation, and close collaboration with ASIC teams to drive feasibility studies and sign‑off. Eligibility includes a bachelor's in engineering and 1+ years of relevant RTL2GDSII experience.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 1+ years of RTL2GDSII physical design or flow development

Responsibilities

• Perform partition synthesis and physical implementation steps
• Develop automation scripts for design steps
• Collaborate with ASIC design team on architectural feasibility and timing targets
• Resolve timing, congestion, and flow issues
• Run STA, noise, and signoff verifications

Skills

RTL2GDSII physical design

EDA tool proficiency

Scripting (Python/Perl/TCL)

Digital design principles

DFT/MBIST knowledge

Team collaboration

Self-driven attitude

Education

Bachelor’s degree in EE/CE/CS

Tools

EDA tools suites

Git/version control

Job description

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to design and implement next‑gen ASICs for Starlink. You will work with cross‑disciplinary teams to push performance, power, and area targets for space and ground infrastructure.

The role emphasizes hands‑on RTL2GDSII flows, scripting automation, and close collaboration with ASIC teams to drive feasibility studies and sign‑off. Eligibility includes a bachelor's in engineering and 1+ years of relevant RTL2GDSII experience.