ASIC Physical Design Engineer (RTL2GDSII)

SpaceX; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space systems. You will work with cross‑disciplinary teams to push physical design from RTL to GDSII, ensuring timing, power and area targets while meeting stringent space‑grade requirements.

This role requires a Bachelor's in ECE/CS, 1+ year RTL2GDSII experience, and strong scripting skills. On-site in Texas with ITAR considerations and a fast‑paced, pioneering environment.

Qualifications

• Experience with RTL2GDSII physical design workflows.
• Strong knowledge of FinFET/CMOS physics.
• Understanding of standard cell libraries and digital design principles.
• Experience with DFT/Scan/MBIST/LBIST and their impact on physical design flows.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Skills

RTL2GDSII physical design

EDA tools

CMOS sub‑micron physics

CMOS digital design

CMOS power dissipation

CMOS analog circuit

DFT/Scan/MBIST/LBIST

Scripting languages

Self-driven attitude

Education

Bachelor’s degree in electrical engineering, computer engineering or computer science

Tools

EDA tools

Job description

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space systems. You will work with cross‑disciplinary teams to push physical design from RTL to GDSII, ensuring timing, power and area targets while meeting stringent space‑grade requirements.

This role requires a Bachelor's in ECE/CS, 1+ year RTL2GDSII experience, and strong scripting skills. On-site in Texas with ITAR considerations and a fast‑paced, pioneering environment.