Remote SI/PI Technical Leader for High‑Speed ASICs

Cisco Systems; Roanoke (TX); Hybride; USD 214 000 - 310 000; Plein temps

Avantages offerts par ce poste

401(k) plan

Paid parental leave

Medical, dental, and vision

Résumé du poste

Cisco Systems is seeking a Signal and Power Integrity Technical Leader to drive next‑generation ASIC packaging. You will lead a specialized SI/PI team to define, design, and verify packaging for Cisco platforms, ensuring power, performance, and area goals are met.

You will mentor engineers, develop 2.5D packaging strategies, and collaborate with layout and system teams to resolve complex technical challenges across interposer, substrate, and PCB levels.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of signal or power integrity experience (or advanced degree with related years).
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics.

Responsabilités

• Lead the Silicon Packaging SI/PI team to define, design and verify ASIC packaging.
• Develop, document, and implement design rules for ultra-high-speed signaling.
• Analyze substrate SI/PI and coordinate with layout for interposer, substrate, and PCB solutions.
• Design and develop ASIC packages for high-volume, high-quality releases with post-layout extraction.
• Mentor junior engineers and collaborate across hardware teams to resolve complex issues.

Connaissances

Signal & Power Integrity

ASIC tape-outs

High-speed SerDes

EMI/EMC concepts

Mentoring teams

Formation

B.S. Electrical Engineering

M.S. Electrical Engineering

PhD Electrical Engineering

Outils

Keysight ADS

Ansys HFSS/EM

Cadence APD

SPICE

Description du poste

Cisco Systems is seeking a Signal and Power Integrity Technical Leader to drive next‑generation ASIC packaging. You will lead a specialized SI/PI team to define, design, and verify packaging for Cisco platforms, ensuring power, performance, and area goals are met.

You will mentor engineers, develop 2.5D packaging strategies, and collaborate with layout and system teams to resolve complex technical challenges across interposer, substrate, and PCB levels.