Remote SI/PI Tech Leader for ASIC Packaging

Cisco Systems; Atlanta (GA); Hybride; USD 214 000 - 310 000; Plein temps

Résumé du poste

Cisco Systems in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to drive the next generation of ASIC packaging and CI/PI strategy. You will mentor engineers, define design rules for ultra‑high‑speed signaling, and collaborate with layout teams across interposers, substrates, and PCBs to optimize performance and yield.

This role offers onsite preference with remote work flexibility, and a compensation package aligned with market ranges for senior SI/PI leadership in

Qualifications

• BS/MS/PhD in EE with 8+ years in SI/PI for ASICs.
• Experience with multiple high‑speed ASIC tape-outs from a packaging perspective.
• Strong knowledge of 56G PAM4, SerDes, channel modeling, and EMI/EMC effects.

Responsabilités

• Define design rules for ultra‑high‑speed signaling to meet power, performance, and area goals.
• Lead SI/PI analysis for substrates, interposers, and PCBs with layout teams.
• Develop ASIC packages for high-volume production including post-layout extraction.
• Mentor junior engineers and promote design-review culture across teams.
• Collaborate with system partners and vendors to resolve complex issues using advanced design rules.

Connaissances

Signal integrity

Power integrity

ASIC packaging

High-speed SerDes

Formation

Bachelor's degree in Electrical Engineering

Outils

Keysight ADS

Ansys HFSS

Cadence APD

Spice simulation

Description du poste

Cisco Systems in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to drive the next generation of ASIC packaging and CI/PI strategy. You will mentor engineers, define design rules for ultra‑high‑speed signaling, and collaborate with layout teams across interposers, substrates, and PCBs to optimize performance and yield.

This role offers onsite preference with remote work flexibility, and a compensation package aligned with market ranges for senior SI/PI leadership in