Remote SI/PI Technical Lead — High-Speed ASIC Packaging

Cisco Systems; Chicago (IL); Hybrid; USD 214,000 - 310,000; Full time

Benefits offered by this job

Remote work option

On-site collaboration

Job summary

Cisco Systems in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to guide our next‑generation ASIC packaging efforts. You will lead a multidisciplinary SI/PI team and drive design rules for ultra‑high‑speed signaling while ensuring power and area goals are met.

Lead SI/PI analyses across interposer, substrate, and PCB, and collaborate with layout to deliver robust, high‑volume ASIC packages with post‑layout extraction.

Qualifications

• Bachelor's/Master's/PhD in Electrical Engineering with extensive SI/PI experience.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Solid understanding of 56G PAM4, SerDes, channel modeling and EMI/EMC concepts.

Responsibilities

• Lead the Silicon Packaging SI/PI team to define and verify ASIC packaging.
• Develop design rules for ultra-high-speed signaling meeting power/performance/area goals.
• Analyze substrate SI/PI and collaborate with layout for optimal solutions.
• Design ASIC packages for high-volume release with post-layout extraction.
• Mentor engineers and promote design reviews and continuous improvement.

Skills

Signal integrity

Power integrity

Team leadership

High-speed signaling

ASIC packaging

Lab experience

SPICE

MATLAB/Python scripting

Raptor-X

Vector Network Analysis

IBIS

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Job description

Cisco Systems in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to guide our next‑generation ASIC packaging efforts. You will lead a multidisciplinary SI/PI team and drive design rules for ultra‑high‑speed signaling while ensuring power and area goals are met.

Lead SI/PI analyses across interposer, substrate, and PCB, and collaborate with layout to deliver robust, high‑volume ASIC packages with post‑layout extraction.