Principal DFT Architect, HBM SoC

Micron Technology, Inc.; Richardson (TX); On-site; USD 146,000 - 309,000; Full time

Job summary

Micron Technology, Inc. is seeking a Principal SoC DFT Engineer in the Heterogeneous Integration Group to own DFT architecture, implementation, and signoff for complex HBM base-die designs.

You will collaborate with RTL, physical design, verification, and product engineering to ensure robust test solutions from pre-silicon through tapeout and bring-up, while guiding flow improvements across teams.

Qualifications

• BSc/BE in Electrical or Computer Engineering or related field.
• 7+ years of SoC/DFT experience in digital ASICs or SoCs.
• Experience with scan, MBIST/LBIST, JTAG/boundary scan, and ATPG.

Responsibilities

• Own SoC-level DFT implementation including scan, MBIST/LBIST, LBIST as applicable, and boundary scan.
• Drive DFT architecture definition early in the design cycle.
• Implement DFT logic at block, subsystem, and full-chip levels.
• Own DFT flow execution and signoff including lint, CDC, DFT rules, ATPG readiness.
• Collaborate with physical design and verification teams for testability and silicon bring-up.
• Support pre-silicon debug and post-silicon yield analysis.

Skills

Scan insertion

MBIST/LBIST

JTAG boundary scan

ATPG concepts

RTL-to-GDS flows

EDA tools (Siemens, Synopsys, Cadence)

Scripting (Python, Tcl, Perl)

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Siemens EDA

Synopsys

Cadence

Job description

Micron Technology, Inc. is seeking a Principal SoC DFT Engineer in the Heterogeneous Integration Group to own DFT architecture, implementation, and signoff for complex HBM base-die designs.

You will collaborate with RTL, physical design, verification, and product engineering to ensure robust test solutions from pre-silicon through tapeout and bring-up, while guiding flow improvements across teams.