Lead SoC DFT Architect for HBM & Bring-Up

Micron Technology, Inc; Folsom (CA); On-site; USD 146,000 - 309,000; Full time

Job summary

Micron Technology, Inc in Folsom, CA is seeking a Principal DFT Engineer to own SoC-level DFT architecture, implement scan, MBIST/LBIST, boundary scan, and ATPG flows for HBM base-die designs through pre-silicon development, tapeout and bring-up.

You will collaborate with RTL, verification, physical design and test teams to optimize DFT for placement, timing and signoff, ensure diagnosability and manufacturability, and participate in post-silicon yield analysis while advancing scalable test

Qualifications

• Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
• Experience with large, complex SoCs involving multiple IPs and subsystems.
• Proficiency with industry-standard EDA tools for DFT and implementation.
• Scripting for flow automation (Python, Tcl, Perl, etc.).

Responsibilities

• Own SoC-level DFT implementation, including scan, MBIST, LBIST, boundary scan, and test access architectures for HBΜ base-die designs.
• Drive DFT architecture definition early in the design cycle aligned with SoC integration, floor planning, timing, power, and physical design constraints.
• Collaborate with RTL and integration teams to implement DFT logic at block, subsystem, and full-chip levels.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Partner with CAD and methodology teams to standardize DFT flows across HBΜ SoC programs.

Skills

DFT architecture

MBIST/LBIST

JTAG/boundary scan

ATPG concepts

RTL-to-GDS flow

Synthesis/STA coordination

EDA tools (Siemens/Synopsys/Cadence)

Scripting (Python/Tcl/Perl)

Large SoCs with multi-IPs

Education

Bachelor’s degree or higher in Electrical/Computer Engineering

Tools

Siemens EDA

Synopsys

Cadence

Job description

Micron Technology, Inc in Folsom, CA is seeking a Principal DFT Engineer to own SoC-level DFT architecture, implement scan, MBIST/LBIST, boundary scan, and ATPG flows for HBM base-die designs through pre-silicon development, tapeout and bring-up.

You will collaborate with RTL, verification, physical design and test teams to optimize DFT for placement, timing and signoff, ensure diagnosability and manufacturability, and participate in post-silicon yield analysis while advancing scalable test