Senior SoC DFT Engineer for HBM

Micron Technology, Inc; Folsom (CA); On-site; USD 146,000 - 247,000; Full time

Job summary

Micron Technology, Inc in the United States is seeking a Staff SoC DFT Engineer for HBM systems. You will own DFT for complex base-die designs, enabling manufacturability, quality, and silicon bring-up across generations.

Work with RTL, CAD, and physical design teams to define DFT architectures, implement scan, MBIST/LBIST, boundary scan, and ATPG, and drive linting, CDC checks, and coverage closure to ensure a robust, scalable test flow for next‑generation memory.

Qualifications

• Strong hands-on experience with SoC DFT architecture and implementation (scan, MBIST/LBIST, boundary scan, ATPG).
• Experience across RTL-to-GDS flows with synthesis, STA, and physical design collaboration.
• Proficiency with industry EDA tools (Siemens, Synopsys, Cadence).
• Bachelor’s degree in Electrical/Computer Engineering or related field, or equivalent.

Responsibilities

• Own SoC-level DFT structures and their implementation (scan, MBIST, LBIST, JTAG, ATPG).
• Define DFT architecture early, aligned with SoC integration, floorplanning, timing, power, and physical design.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL/SoC teams.
• Complete and sign off DFT flows: linting, CDC checks, ATPG readiness, coverage closure.
• Collaborate with physical design to optimize DFT for placement, routing, timing, DRC/LVS.
• Work with verification, test, and manufacturing to ensure testability and post-silicon bring-up.
• Partner with CAD/methodology teams to standardize DFT flows and mentor engineers.

Skills

SoC DFT

MBIST/LBIST

JTAG boundary scan

ATPG

RTL-to-GDS flow

Education

Bachelor’s degree in Electrical or Computer Engineering or related field

Tools

Siemens

Synopsys

Cadence

Job description

Micron Technology, Inc in the United States is seeking a Staff SoC DFT Engineer for HBM systems. You will own DFT for complex base-die designs, enabling manufacturability, quality, and silicon bring-up across generations.

Work with RTL, CAD, and physical design teams to define DFT architectures, implement scan, MBIST/LBIST, boundary scan, and ATPG, and drive linting, CDC checks, and coverage closure to ensure a robust, scalable test flow for next‑generation memory.