Principal SoC DFT Architect for HBM

Micron Memory Malaysia Sdn Bhd; Folsom (CA); On-site; USD 146,000 - 309,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Job summary

Micron Technology seeks a Principal DFT Engineer in Folsom, CA to own DFT for HBM base-die SoCs, drive architecture, and signoff across RTL, synthesis, and physical design. Collaborate with RTL, verification, and test teams to ensure robust testability and manufacturability from pre-silicon to bring-up.

The role requires 7+ years in SoC DFT/implementation, experience with scan, MBIST/LBIST, JTAG, and ATPG, and proficiency with industry EDA tools. Competitive base salary packaged with benefits.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.

Responsibilities

• Own SoC-level DFT implementation, including scan, MBIST, LBIST, boundary scan, and test access architectures for HBM base-die designs.
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, timing closure, and DRC/LVS signoff.
• Support pre-silicon debug of DFT issues and assist with post-silicon bring-up and yield/debug analysis.

Skills

Scan insertion

MBIST/LBIST

JTAG/boundary scan

ATPG concepts

RTL-to-GDS flows

Scripting (Python, Tcl, Perl)

Education

Bachelor’s degree or higher in Electrical/Computer Engineering or related field

Tools

Siemens EDA

Synopsys

Cadence

Job description

Micron Technology seeks a Principal DFT Engineer in Folsom, CA to own DFT for HBM base-die SoCs, drive architecture, and signoff across RTL, synthesis, and physical design. Collaborate with RTL, verification, and test teams to ensure robust testability and manufacturability from pre-silicon to bring-up.

The role requires 7+ years in SoC DFT/implementation, experience with scan, MBIST/LBIST, JTAG, and ATPG, and proficiency with industry EDA tools. Competitive base salary packaged with benefits.