HBM SoC DFT Engineer — Pioneering Test & Bring‑Up

Micron Technology, Inc.; Folsom (CA); On-site; USD 199,000 - 347,000; Full time

Benefits offered by this job

Medical/Dental/Vision

Paid Time Off

Equity & Bonuses

Job summary

Micron Technology, Inc. is seeking an experienced DFT/SoC design engineer to own DFT architectures for high-bandwidth memory SoCs.

You will drive early DFT decisions, implement test logic across blocks and full-chip levels, and ensure seamless pre-silicon debug and post-silicon bring-up in collaboration with RTL, STA, and physical design teams. The role emphasizes close collaboration with verification, test, and manufacturing groups, with opportunities to mentor others and apply Gen-AI

Qualifications

• Strong hands-on experience with SoC DFT architecture and implementation (scan/MBIST/LBIST/JTAG/ATPG).
• Experience across RTL-to-GDS flows with synthesis, STA, and physical design teams.
• Proficiency with industry-standard EDA tools for DFT (Siemens, Synopsys, Cadence).
• Bachelor’s degree in Electrical or Computer Engineering, or equivalent practical experience.
• 10+ years of relevant SoC DFT/implementation experience.

Responsibilities

• Own SoC-level DFT structures and their implementation (scan, MBIST, LBIST, JTAG).
• Define and drive DFT architecture early in the design cycle.
• Implement DFT logic at block, subsystem, and full-chip levels with RTL/SoC teams.
• Complete and sign off DFT flows including ATPG readiness and coverage closure.
• Collaborate with physical design to optimize DFT for placement, routing, and DRC/LVS signoff.
• Work with verification, test, and manufacturing teams to ensure testability and pre/post-silicon bring-up.
• Mentor engineers and drive innovation for future HBM generations.

Skills

SoC DFT architecture

RTL-to-GDS flows

ATPG/JTAG/MBIST/LBIST

EDA tools (Siemens/Synopsys/Cadence)

Education

B.S. in Electrical/Computer Engineering

Tools

Siemens

Synopsys

Cadence

Job description

Micron Technology, Inc. is seeking an experienced DFT/SoC design engineer to own DFT architectures for high-bandwidth memory SoCs.

You will drive early DFT decisions, implement test logic across blocks and full-chip levels, and ensure seamless pre-silicon debug and post-silicon bring-up in collaboration with RTL, STA, and physical design teams. The role emphasizes close collaboration with verification, test, and manufacturing groups, with opportunities to mentor others and apply Gen-AI