Principal DFT Engineer — HBM SoC Testing

Micron Technology, Inc; Folsom (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Micron Technology, Inc in Folsom, California is seeking a Principal DFT Engineer to lead DFT implementation and architecture definition for HBM base-die designs. Candidates should have 7+ years of experience in SoC design and a Bachelor's degree in Electrical Engineering or Computer Engineering.

The successful candidate will work closely with various teams to ensure testability and smooth silicon bring-up using advanced EDA tools. We promote equal opportunity and welcome applicants from diverse backgrounds.

Qualifications

• 7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.

Responsibilities

• Own SoC-level DFT implementation, including scan, MBIST, LBIST.
• Drive DFT architecture definition early in the design cycle.
• Implement and integrate DFT logic at the block and full-chip levels.
• Collaborate with physical design teams for optimization.

Skills

Experience with scan insertion

MBIST/LBIST architectures

JTAG/boundary scan

ATPG concepts

Familiarity with full RTL-to-GDS SoC flows

Proficiency with industry-standard EDA tools

Scripting languages (Python, Tcl, Perl)

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

EDA tools from Siemens

EDA tools from Synopsys

EDA tools from Cadence

Job description

Micron Technology, Inc in Folsom, California is seeking a Principal DFT Engineer to lead DFT implementation and architecture definition for HBM base-die designs. Candidates should have 7+ years of experience in SoC design and a Bachelor's degree in Electrical Engineering or Computer Engineering.

The successful candidate will work closely with various teams to ensure testability and smooth silicon bring-up using advanced EDA tools. We promote equal opportunity and welcome applicants from diverse backgrounds.