Senior SoC DFT Engineer – HBM Test Architect

Micron Technology; Folsom (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Micron Technology in California is seeking an experienced design-for-test (DFT) lead for high‑bandwidth memory (HBM) SoC base‑die designs. You will own DFT architecture, implement scan, MBIST/LBIST, and JTAG, and collaborate with RTL, synthesis, and physical design to enable manufacturability and silicon bring‑up.

The role emphasizes early DFT definition, CDC checks, ATPG readiness, and cross‑group reviews, with mentoring for engineers and contributions to future HBM generations.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience.
• Seven or more years of experience in SoC design, DFT, or implementation for complex digital ASICs/SoCs.
• Experience across RTL-to-GDS flows and collaboration with RTL, synthesis, STA and physical design teams.

Responsibilities

• Own SoC-level DFT architecture and implementation, including scan, MBIST/LBIST, boundary scan (JTAG), and test access for HBM base-die designs.
• Define and drive DFT architecture early in the design cycle, aligning with SoC integration, floorplanning, timing, power, and physical requirements.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels with RTL and SoC integration teams.
• Execute and sign off DFT flows, including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, timing closure, and DRC/LVS signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability and pre/post‑silicon bring‑up.
• Mentor engineers and contribute to cross‑group technical reviews while driving innovations for future HBM generations.

Skills

DFT architecture

MBIST/LBIST

JTAG boundary scan

ATPG

RTL-to-GDS flow

EDA tools

SoC design experience

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synthesis tools

STA tools

Physical design tools

Job description

Micron Technology in California is seeking an experienced design-for-test (DFT) lead for high‑bandwidth memory (HBM) SoC base‑die designs. You will own DFT architecture, implement scan, MBIST/LBIST, and JTAG, and collaborate with RTL, synthesis, and physical design to enable manufacturability and silicon bring‑up.

The role emphasizes early DFT definition, CDC checks, ATPG readiness, and cross‑group reviews, with mentoring for engineers and contributions to future HBM generations.