HBM SoC DFT Engineer for AI/ML Systems

Micron Technology, Inc.; Richardson (TX); On-site; USD 199,000 - 347,000; Full time

Benefits offered by this job

Medical, dental & vision

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. invites a senior DFT engineer to own SoC‑level DFT structures for complex HBM base‑die designs. You will drive DFT architecture, implement and integrate test logic across blocks to full chip and work with RTL, synthesis and physical design teams for timing and sign‑off.

You will apply advanced ATPG, MBIST/LBIST concepts and boundary scan while mentoring engineers and exploring Gen‑AI driven improvements to DFT workflows in a fast‑paced AI/ML focused environment.

Qualifications

• Strong hands‑on experience with SoC develop for test (DFT) architecture and implementation, including scan and MBIST/LBIST concepts.
• Experience across RTL‑to‑GDS SoC flows and collaboration with synthesis, STA, and physical design teams.
• Proficiency with industry‑standard EDA tools for DFT and implementation.

Responsibilities

• Own SoC‑level DFT structures and their implementation across RTL to GDS.
• Define and drive DFT architecture early in the design cycle.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels.
• Complete and sign off DFT flows including ATPG readiness and coverage closure.
• Collaborate with physical design to optimize DFT for placement and timing.
• Work with cross‑functional teams to ensure testability and post‑silicon bring‑up.
• Mentor engineers and drive innovative DFT approaches for future HBM generations.

Skills

DFT architecture

MBIST/LBIST

JTAG boundary scan

ATPG

RTL-to-GDS

EDA tools (Siemens/Synopsys/Cadence)

Python scripting

HBM memory systems

RTL debugging

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

Siemens EDA

Synopsys

Cadence

Job description

Micron Technology, Inc. invites a senior DFT engineer to own SoC‑level DFT structures for complex HBM base‑die designs. You will drive DFT architecture, implement and integrate test logic across blocks to full chip and work with RTL, synthesis and physical design teams for timing and sign‑off.

You will apply advanced ATPG, MBIST/LBIST concepts and boundary scan while mentoring engineers and exploring Gen‑AI driven improvements to DFT workflows in a fast‑paced AI/ML focused environment.