Principal DFT Engineer, SoC-HBM (Equity Eligible)

Micron Technology, Inc.; Folsom (CA); On-site; USD 146,000 - 309,000; Full time

Benefits offered by this job

Equity

Bonuses

Benefits package

Job summary

Micron Technology is seeking a Principal SoC DFT Engineer in the Heterogeneous Integration Group to lead DFT architecture, implementation, and signoff for complex HBM base-die designs. You will collaborate with RTL, verification, physical design, and product engineering to ensure robust test solutions from pre-silicon through tapeout.

The role requires 7+ years in SoC development, DFT, or implementation, with expertise in scan, MBIST/LBIST, JTAG, and ATPG concepts.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of proven experience in SoC development, DFT, or implementation for complex digital ASICs or SoCs.

Responsibilities

• Own SoC-level DFT implementation (scan, MBIST, LBIST, boundary scan, test access) for HBM base-die designs.
• Drive DFT architecture early in design cycle coordinating with SoC integration, floorplanning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL/integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rules, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability and silicon bring-up.

Skills

DFT architecture

MBIST/LBIST

JTAG/boundary scan

Python/Tcl/Perl

EDA tools (Siemens/Synopsys/Cadence)

Education

Bachelor’s degree or higher in Electrical/Computer Engineering

Tools

RTL-to-GDS flow

Scripting for flow automation

Job description

Micron Technology is seeking a Principal SoC DFT Engineer in the Heterogeneous Integration Group to lead DFT architecture, implementation, and signoff for complex HBM base-die designs. You will collaborate with RTL, verification, physical design, and product engineering to ensure robust test solutions from pre-silicon through tapeout.

The role requires 7+ years in SoC development, DFT, or implementation, with expertise in scan, MBIST/LBIST, JTAG, and ATPG concepts.